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Mentor Graphics to Deliver Co-Verification Support for Altera's ARM and MIPS-based Excalibur Embedded Processor Designs

WILSONVILLE, Ore.--(BUSINESS WIRE)--April 12, 2001-- Mentor Graphics Corp. (Nasdaq:MENT), the market and technology leader for hardware/software co-verification, and Altera® Corp., (Nasdaq:ALTR), a leading supplier of programmable logic devices, have agreed to deliver customized co-verification processor support packages (PSPs) for Altera's ARM®-based and MIPS®-based Excalibur(TM) embedded processor solutions. This is the first solution in a broader initiative announced April 10 at the Embedded Systems Conference (``Mentor Graphics and Altera Unveil Strategy to Speed Industry Move to Systems-on-a Programmable Chip''). The agreement will result in an unprecedented time-to-market advantage for systems designers by ensuring early insight into design issues and allowing software and hardware design to occur concurrently.

The new Excalibur PSPs are designed to work with Mentor's Seamless® Co-Verification Environment(TM) (CVE). The first deliverable of this partnership program will be the Excalibur ARM PSP and the associated memory models in the Excalibur ARM922 stripe.

The ARM-based Excalibur System-On-a-Programmable-Chip (SOPC) family combines an ARM922 embedded processor, programmable logic, memory, and key system peripherals to create a complete embedded system solution. Co-verification tools from Mentor's Seamless® CVE and the Excalibur ARM PSP will allow systems designers to validate the hardware and software interfaces in a virtual prototype environment, while both designs are still in progress.

``Co-verification is a proven methodology for better simulation and system-level debugging. It enables shortening of overall design cycles by increasing the chance of first time success,'' said Jordan Plofsky, Senior Vice President of Embedded Processor Products at Altera. ``With Mentor's Seamless CVE and the Excalibur ARM PSP, our customers can verify the cores within Excalibur devices and the external interfaces to off-chip components during their design and debug phases, further increasing their productivity.''

The Excalibur ARM PSP is an extension of Mentor's existing cycle-accurate co-verification model of the ARM9 family already in widespread use. The PSP is tailored for ARM-based Excalibur designs to facilitate adoption by Altera customers. The PSP works with Mentor's XRAY® high-level debugger and supports all popular logic simulation platforms, including Model Technology's ModelSim® simulation product.

``With traditional ASIC embedded processors being used within programmable logic, Seamless becomes as essential in programmable platform design as it is in ASIC System-on-Chip methodologies,'' said Serge Leef, general manager, Mentor Graphics system-on-chip verification business unit. ``As additional embedded processor cores are optimized for and integrated with Altera programmable logic architectures, Mentor Graphics will continue to be first-to-market with complete co-verification model support.''

Pricing and Availability

The PSP for Altera ARM-based Excalibur designs are available now on HP and Sun workstations directly from Mentor Graphics. For more information, including pricing, or to register for a free Seamless workshop, visit Mentor's Web site at www.mentor.com/seamless.

About Mentor Graphics Seamless CVE

Combining the best in embedded software development tools with logic simulation, Mentor Graphics' Seamless co-verification environment delivers high performance co-verification months before a hardware prototype can be built. The Seamless environment enables software and hardware development to be parallel activities, removing the software from the critical path, and reducing the risk of hardware prototype iterations resulting from integration errors. User-controlled optimizations boost performance by isolating the logic simulator from software-intensive operations such as block memory transfers and algorithmic routines.

About Altera's Excalibur Embedded Processor Solutions

Combining logic, memory, and a processor core, Altera's new Excalibur embedded processor solutions allow engineers to integrate an entire system on a single programmable logic device (PLD). The three families -- the Nios(TM) soft core embedded processor, the ARM-based hard core embedded processor, and the MIPS-based hard core embedded processor -- offer the flexibility of processor cores with the integration of system-on-a-programmable-chip (SOPC) logic.

Excalibur embedded processors can be used in any application requiring processors and PLDs with gate counts up to 1,000,000 gates. They offer full integration with Altera's APEX(TM) PLD architecture, and are supported by the QuartusII(TM) development tool, which is optimized for the Excalibur embedded processor families.

About Altera Corporation

Altera Corporation, The Programmable Solutions Company®, was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. Altera common stock is traded on The Nasdaq Stock Market under the symbol ALTR. More information on Altera is available on the Internet at: http://www.altera.com.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of nearly $600 million and employs approximately 2,750 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Ore. 97070-7777. Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, Calif. 95131-2314. World Wide Web site: www.mentor.com.

Altera, The Programmable Solutions Company, Excalibur, Nios, Quartus, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other trademarks are the property of their respective holders.

Mentor Graphics, XRAY, Seamless, Calibre, xCalibre and Modelsim are registered trademarks of Mentor Graphics Corporation. Co-Verification Environment (CVE) is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.


Contact:
     Mentor Graphics
     Wendy Slocum, 503/685-1145
     wendy_slocum@mentor.com
      or
     Benjamin Group/BSMG Worldwide
     Victor Domine, 408/559-6090 (Media Relations Contact)
     victor_domine@benjamingroup.com
      or
     Altera
     Bruce Fienberg, 408/544-6866
     bfienber@altera.com

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